{"id":1721,"date":"2022-02-11T07:00:39","date_gmt":"2022-02-10T22:00:39","guid":{"rendered":"https:\/\/www.xlsoft.com\/jp\/blog\/intel\/?p=1721"},"modified":"2022-03-30T07:45:35","modified_gmt":"2022-03-29T22:45:35","slug":"explore-dpcpp-through-intel-fpga-code-samples","status":"publish","type":"post","link":"https:\/\/www.xlsoft.com\/jp\/blog\/intel\/2022\/02\/11\/explore-dpcpp-through-intel-fpga-code-samples\/","title":{"rendered":"\u30a4\u30f3\u30c6\u30eb FPGA \u30b3\u30fc\u30c9\u30b5\u30f3\u30d7\u30eb\u3067 DPC++ \u3092\u5b66\u3076"},"content":{"rendered":"<h2><span style=\"font-family: arial, helvetica, sans-serif;\"> \u306f\u3058\u3081\u306b<\/span><\/h2>\n<p><span style=\"font-family: arial, helvetica, sans-serif;\">\u3053\u306e\u30ac\u30a4\u30c9\u306f\u3001\u6b21\u306e\u3053\u3068\u3092\u7406\u89e3\u3057\u3066\u3044\u305f\u3060\u304f\u3053\u3068\u3092\u76ee\u7684\u3068\u3057\u3066\u3044\u307e\u3059\u3002<\/span><\/p>\n<ul>\n<li><span style=\"font-family: arial, helvetica, sans-serif;\">\u30a4\u30f3\u30c6\u30eb<sup>\u00ae<\/sup> FPGA DPC++ \u306e\u30b3\u30fc\u30c9\u30b5\u30f3\u30d7\u30eb\u3092\u3001\u8907\u96d1\u3055\u3068\u30e6\u30fc\u30b9\u30b1\u30fc\u30b9\u3092\u8e0f\u307e\u3048\u3066\u9996\u5c3e\u4e00\u8cab\u3057\u305f\u65b9\u6cd5\u3067\u30ca\u30d3\u30b2\u30fc\u30c8\u3059\u308b\u65b9\u6cd5\u3002<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif;\">6 \u3064\u306e\u30a8\u30c3\u30bb\u30f3\u30b7\u30e3\u30eb FPGA \u30b3\u30fc\u30c9\u30b5\u30f3\u30d7\u30eb\u3092\u4f7f\u3063\u3066\u3001FPGA \u4e0a\u3067\u6700\u521d\u306e oneAPI \u30a2\u30d7\u30ea\u30b1\u30fc\u30b7\u30e7\u30f3\u3092\u5b9f\u73fe\u3059\u308b\u65b9\u6cd5\u3002<\/span><\/li>\n<\/ul>\n<p><span style=\"font-family: arial, helvetica, sans-serif;\"><a href=\"https:\/\/github.com\/oneapi-src\/oneAPI-samples\/tree\/master\/DirectProgramming\/DPC%2B%2BFPGA\/Tutorials\" target=\"_blank\" rel=\"noopener\">DPC++ FPGA \u30c1\u30e5\u30fc\u30c8\u30ea\u30a2\u30eb<\/a> (\u82f1\u8a9e) \u306e\u30d5\u30a9\u30eb\u30c0\u30fc\u9593\u306e\u79fb\u52d5\u306b\u306f\u3001\u30c1\u30e5\u30fc\u30c8\u30ea\u30a2\u30eb\u9593\u306e\u4f9d\u5b58\u95a2\u4fc2\u3092\u793a\u3057\u305f\u4ee5\u4e0b\u306e\u56f3\u3092\u4f7f\u7528\u3057\u3066\u304f\u3060\u3055\u3044\u3002<\/span><\/p>\n<p><span style=\"font-family: arial, helvetica, sans-serif;\">\u6ce8: \u300e\u30a4\u30f3\u30c6\u30eb<sup>\u00ae<\/sup> oneAPI DPC++ FPGA \u6700\u9069\u5316\u30ac\u30a4\u30c9\u300f\u306e\u300c<a href=\"https:\/\/www.intel.com\/content\/www\/us\/en\/develop\/documentation\/oneapi-fpga-optimization-guide\/top\/introduction-to-fpga-design-concepts.html\" target=\"_blank\" rel=\"noopener\">\u7b2c 1 \u7ae0: FPGA \u30c7\u30b6\u30a4\u30f3\u30b3\u30f3\u30bb\u30d7\u30c8\u5165\u9580<\/a> (\u82f1\u8a9e)\u300d\u306f\u3001FPGA \u306e\u57fa\u672c\u7684\u306a\u30b3\u30f3\u30bb\u30d7\u30c8\u306b\u3064\u3044\u3066\u8aac\u660e\u3057\u3066\u304a\u308a\u3001\u3059\u3079\u3066\u306e FPGA \u56fa\u6709\u306e\u30b3\u30fc\u30c9\u30b5\u30f3\u30d7\u30eb\u306e\u524d\u63d0\u6761\u4ef6\u3068\u306a\u3063\u3066\u3044\u307e\u3059\u3002<\/span><\/p>\n<p><span style=\"font-family: arial, helvetica, sans-serif;\"><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter size-full wp-image-1725\" src=\"https:\/\/www.xlsoft.com\/jp\/blog\/intel\/wp-content\/uploads\/sites\/5\/2022\/02\/intel_blog.jpg\" alt=\"\" width=\"1392\" height=\"752\" srcset=\"https:\/\/www.xlsoft.com\/jp\/blog\/intel\/wp-content\/uploads\/sites\/5\/2022\/02\/intel_blog.jpg 1392w, https:\/\/www.xlsoft.com\/jp\/blog\/intel\/wp-content\/uploads\/sites\/5\/2022\/02\/intel_blog-300x162.jpg 300w, https:\/\/www.xlsoft.com\/jp\/blog\/intel\/wp-content\/uploads\/sites\/5\/2022\/02\/intel_blog-768x415.jpg 768w, https:\/\/www.xlsoft.com\/jp\/blog\/intel\/wp-content\/uploads\/sites\/5\/2022\/02\/intel_blog-1024x553.jpg 1024w\" sizes=\"auto, (max-width: 1392px) 100vw, 1392px\" \/><\/span><\/p>\n<h2><span style=\"font-family: arial, helvetica, sans-serif;\">\u30a8\u30c3\u30bb\u30f3\u30b7\u30e3\u30eb FPGA \u30b3\u30fc\u30c9\u30b5\u30f3\u30d7\u30eb<\/span><\/h2>\n<p><span style=\"font-family: arial, helvetica, sans-serif;\">\u4ee5\u4e0b\u306e FPGA \u30b5\u30f3\u30d7\u30eb\u306f\u3001FPGA \u3067\u6700\u521d\u306e oneAPI \u30a2\u30d7\u30ea\u30b1\u30fc\u30b7\u30e7\u30f3\u3092\u59cb\u3081\u308b\u306e\u306b\u9069\u3057\u305f\u6709\u7528\u306a\u30c1\u30e5\u30fc\u30c8\u30ea\u30a2\u30eb\u306e\u30bb\u30ec\u30af\u30b7\u30e7\u30f3\u3067\u3059\u3002<\/span><\/p>\n<h2><span style=\"font-family: arial, helvetica, sans-serif;\">\u524d\u63d0\u6761\u4ef6<\/span><\/h2>\n<ul>\n<li><span style=\"font-family: arial, helvetica, sans-serif;\">Khronos* \u30b0\u30eb\u30fc\u30d7\u306b\u3088\u308b\u300cSYCL 2020 Provisional Specification\u300d\u306b\u8a18\u8f09\u3055\u308c\u3066\u3044\u308b SYCL* \u306e\u30b3\u30f3\u30bb\u30d7\u30c8\u3068\u30a2\u30d7\u30ea\u30b1\u30fc\u30b7\u30e7\u30f3\u30fb\u30d7\u30ed\u30b0\u30e9\u30df\u30f3\u30b0\u30fb\u30a4\u30f3\u30bf\u30fc\u30d5\u30a7\u30fc\u30b9 (API) \u306b\u3064\u3044\u3066\u3059\u3067\u306b\u3054\u5b58\u77e5\u3067\u3042\u308b\u3053\u3068\u3002SYCL* \u8a00\u8a9e\u306e\u5b66\u7fd2\u306b\u306f\u3001\u30aa\u30fc\u30d7\u30f3\u30a2\u30af\u30bb\u30b9\u306e\u66f8\u7c4d\u300c<a href=\"https:\/\/link.springer.com\/book\/10.1007\/978-1-4842-5574-2\" target=\"_blank\" rel=\"noopener\"> \u30c7\u30fc\u30bf\u4e26\u5217 C++: C++ \u3068 SYCL \u3092\u4f7f\u3063\u305f\u30d8\u30c6\u30ed\u30b8\u30cb\u30a2\u30b9\u30fb\u30b7\u30b9\u30c6\u30e0\u30fb\u30d7\u30ed\u30b0\u30e9\u30df\u30f3\u30b0\u306e\u305f\u3081\u306e DPC++ \u3092\u30de\u30b9\u30bf\u30fc\u3059\u308b <\/a> (\u82f1\u8a9e)\u300d\u3092\u304a\u52e7\u3081\u3057\u307e\u3059\u3002\u8a73\u3057\u304f\u306f\u3001<a href=\"&quot;chrome-extension:\/\/efaidnbmnnnibpcajpcglclefindmkaj\/viewer.html?pdfurl=https%3A%2F%2Fwww.khronos.org%2Fregistry%2FSYCL%2Fspecs%2Fsycl-1.2.1.pdf&amp;chunk=true\" target=\"_blank\" rel=\"noopener\"> SYCL* \u4ed5\u69d8\u66f8\u30d0\u30fc\u30b8\u30e7\u30f3 2.1 <\/a>(\u82f1\u8a9e) \u3092\u53c2\u7167\u3057\u3066\u304f\u3060\u3055\u3044\u3002<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif;\">SYCL* \u30a2\u30d7\u30ea\u30b1\u30fc\u30b7\u30e7\u30f3\u3092\u4f5c\u6210\u3057\u305f\u7d4c\u9a13\u304c\u3042\u308b\u3053\u3068\u3002\u8a73\u7d30\u306b\u3064\u3044\u3066\u306f\u3001\u300e<a href=\"https:\/\/www.intel.com\/content\/www\/us\/en\/develop\/documentation\/oneapi-programming-guide\/top.html\" target=\"_blank\" rel=\"noopener\">\u30a4\u30f3\u30c6\u30eb<sup>\u00ae<\/sup> oneAPI \u30d7\u30ed\u30b0\u30e9\u30df\u30f3\u30b0\u30fb\u30ac\u30a4\u30c9<\/a> (\u82f1\u8a9e)\u300f\u3092\u53c2\u7167\u3057\u3066\u304f\u3060\u3055\u3044\u3002<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif;\">FPGA \u3067\u958b\u767a\u3059\u308b\u5834\u5408\u306b\u63a8\u5968\u3055\u308c\u308b\u300e\u30a4\u30f3\u30c6\u30eb<sup>\u00ae<\/sup> oneAPI DPC++ FPGA \u6700\u9069\u5316\u30ac\u30a4\u30c9\u300f\u306e\u300c<a href=\"https:\/\/www.intel.com\/content\/www\/us\/en\/develop\/documentation\/oneapi-fpga-optimization-guide\/top\/introduction-to-fpga-design-concepts.html\" target=\"_blank\" rel=\"noopener\">\u7b2c 1 \u7ae0: FPGA \u30c7\u30b6\u30a4\u30f3\u30b3\u30f3\u30bb\u30d7\u30c8\u5165\u9580<\/a> (\u82f1\u8a9e)\u300d\u3092\u304a\u8aad\u307f\u306b\u306a\u3063\u3066\u3044\u308b\u3053\u3068\u3002FPGA \u30c1\u30e5\u30fc\u30c8\u30ea\u30a2\u30eb\u306e\u307b\u3068\u3093\u3069\u3092\u7406\u89e3\u3059\u308b\u305f\u3081\u306e\u524d\u63d0\u6761\u4ef6\u3067\u3082\u3042\u308a\u307e\u3059\u3002FPGA \u7528\u30c7\u30fc\u30bf\u4e26\u5217 C++ (DPC++) \u30a2\u30d7\u30ea\u30b1\u30fc\u30b7\u30e7\u30f3\u306e\u6027\u80fd\u3092\u6700\u5927\u9650\u306b\u5f15\u304d\u51fa\u3059\u306b\u306f\u3001\u57fa\u76e4\u3068\u306a\u308b\u30cf\u30fc\u30c9\u30a6\u30a7\u30a2\u306b\u7cbe\u901a\u3057\u3001DPC++ \u30a2\u30d7\u30ea\u30b1\u30fc\u30b7\u30e7\u30f3\u3092 FPGA \u306b\u5909\u63db\u304a\u3088\u3073\u30de\u30c3\u30d4\u30f3\u30b0\u3059\u308b\u30b3\u30f3\u30d1\u30a4\u30e9\u30fc\u306e\u6700\u9069\u5316\u306b\u3064\u3044\u3066\u7406\u89e3\u3059\u308b\u5fc5\u8981\u304c\u3042\u308a\u307e\u3059\u3002<\/span><\/li>\n<\/ul>\n<h2><span style=\"font-family: arial, helvetica, sans-serif;\">\u30b5\u30f3\u30d7\u30eb\u30fb\u30d7\u30ed\u30b8\u30a7\u30af\u30c8\u306e\u30d3\u30eb\u30c9\u3068\u5b9f\u884c<\/span><\/h2>\n<p><span style=\"font-family: arial, helvetica, sans-serif;\">FPGA \u30c1\u30e5\u30fc\u30c8\u30ea\u30a2\u30eb\u3092\u30b3\u30f3\u30d1\u30a4\u30eb\u3059\u308b\u306b\u306f\u3001<a href=\"https:\/\/www.xlsoft.com\/jp\/products\/intel\/oneapi\/index.html\" target=\"_blank\" rel=\"noopener\">\u30a4\u30f3\u30c6\u30eb<sup>\u00ae<\/sup> oneAPI \u30d9\u30fc\u30b9\u30fb\u30c4\u30fc\u30eb\u30ad\u30c3\u30c8<\/a>\u3068<a href=\"https:\/\/www.xlsoft.com\/jp\/products\/intel\/oneapi\/fpga\/index.html\" target=\"_blank\" rel=\"noopener\"> oneAPI \u30d9\u30fc\u30b9\u30fb\u30c4\u30fc\u30eb\u30ad\u30c3\u30c8\u7528\u30a4\u30f3\u30c6\u30eb<sup>\u00ae<\/sup> FPGA \u30a2\u30c9\u30aa\u30f3<\/a>\u3092\u30c0\u30a6\u30f3\u30ed\u30fc\u30c9\u3057\u3066\u30a4\u30f3\u30b9\u30c8\u30fc\u30eb\u3059\u308b\u304b\u3001\u30a4\u30f3\u30c6\u30eb<sup>\u00ae<\/sup> DevCloud for oneAPI \u306e\u30a2\u30ab\u30a6\u30f3\u30c8\u3092\u53d6\u5f97\u3059\u308b\u5fc5\u8981\u304c\u3042\u308a\u307e\u3059\u3002<\/span><\/p>\n<p><span style=\"font-family: arial, helvetica, sans-serif;\">\u30b3\u30de\u30f3\u30c9\u30e9\u30a4\u30f3\u30fb\u30a4\u30f3\u30bf\u30fc\u30d5\u30a7\u30a4\u30b9 (CLI) \u307e\u305f\u306f\u7d71\u5408\u958b\u767a\u74b0\u5883 (IDE) \u3092\u4f7f\u7528\u3057\u3066\u3001\u30a4\u30f3\u30c6\u30eb<sup>\u00ae<\/sup> oneAPI \u30d9\u30fc\u30b9\u30fb\u30c4\u30fc\u30eb\u30ad\u30c3\u30c8\u306e\u30ac\u30a4\u30c9\u3092\u958b\u59cb\u3059\u308b\u306b\u306f\u3001\u6b21\u306e\u30ea\u30f3\u30af\u3092\u53c2\u7167\u3057\u3066\u304f\u3060\u3055\u3044\u3002<\/span><\/p>\n<ul>\n<li><span style=\"font-family: arial, helvetica, sans-serif;\">\u30b3\u30de\u30f3\u30c9\u30e9\u30a4\u30f3\u3092\u4f7f\u3063\u3066\u30b5\u30f3\u30d7\u30eb\u30fb\u30d7\u30ed\u30b8\u30a7\u30af\u30c8\u3092\u30d3\u30eb\u30c9\u3057\u3066\u5b9f\u884c\u3059\u308b\u3002<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif;\">Linux*<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif;\">Windows*<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif;\">IDE \u3092\u4f7f\u3063\u3066\u30b5\u30f3\u30d7\u30eb\u30fb\u30d7\u30ed\u30b8\u30a7\u30af\u30c8\u3092\u30d3\u30eb\u30c9\u3057\u3066\u5b9f\u884c\u3059\u308b\u3002<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif;\">Linux* (Eclipse* \u3082\u3057\u304f\u306f Visual Studio* \u30b3\u30fc\u30c9)<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif;\">Windows* (Visual Studio*)<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif;\">GitHub* (\u5404 FPGA \u30b5\u30f3\u30d7\u30eb\u306b\u306f\u3001\u7279\u5b9a\u306e Git \u30ea\u30dd\u30b8\u30c8\u30ea\u30fc\u3078\u306e\u30ea\u30f3\u30af\u304c\u3042\u308a\u307e\u3059\u3002\u8a73\u7d30\u306f\u4ee5\u4e0b\u306e\u30bb\u30af\u30b7\u30e7\u30f3\u3092\u53c2\u7167\u3057\u3066\u304f\u3060\u3055\u3044\u3002)<\/span><\/li>\n<\/ul>\n<h3><span style=\"font-family: arial, helvetica, sans-serif;\">\u30b5\u30f3\u30d7\u30eb 1\uff1aFPGA \u30b3\u30f3\u30d1\u30a4\u30eb\u30d5\u30ed\u30fc<\/span><\/h3>\n<p><span style=\"font-family: arial, helvetica, sans-serif;\">\u3053\u306e\u30b5\u30f3\u30d7\u30eb\u3067\u306f\u3001\u30a4\u30f3\u30c6\u30eb<sup>\u00ae<\/sup> FPGA \u30c7\u30d0\u30a4\u30b9\u3092\u30bf\u30fc\u30b2\u30c3\u30c8\u3068\u3057\u305f\u6700\u3082\u4e00\u822c\u7684\u306a\u30b3\u30f3\u30d1\u30a4\u30eb\u30d5\u30ed\u30fc\u3092\u7d39\u4ecb\u3057\u3001\u5404\u30d5\u30ed\u30fc\u3092\u4f7f\u7528\u3059\u308b\u30bf\u30a4\u30df\u30f3\u30b0\u3092\u8aac\u660e\u3057\u307e\u3059\u3002<\/span><\/p>\n<table style=\"height: 60px; width: 661px;\" width=\"590\">\n<tbody>\n<tr>\n<td style=\"width: 313.479px;\"><span style=\"font-family: arial, helvetica, sans-serif;\">CLI \u307e\u305f\u306f IDE \u30b5\u30f3\u30d7\u30eb\u540d<\/span><\/td>\n<td style=\"width: 331.521px;\"><span style=\"font-family: arial, helvetica, sans-serif;\">Git \u30ea\u30dd\u30b8\u30c8\u30ea\u30fc\u3078\u306e\u30ea\u30f3\u30af<\/span><\/td>\n<\/tr>\n<tr>\n<td style=\"width: 313.479px;\"><span style=\"font-family: arial, helvetica, sans-serif;\">fpga_compile<\/span><\/td>\n<td style=\"width: 331.521px;\"><span style=\"font-family: arial, helvetica, sans-serif;\"><a href=\"https:\/\/github.com\/oneapi-src\/oneAPI-samples\/tree\/master\/DirectProgramming\/DPC%2B%2BFPGA\/Tutorials\/GettingStarted\/fpga_compile\" target=\"_blank\" rel=\"noopener\">FPGA \u30b3\u30f3\u30d1\u30a4\u30eb\u306e\u30b5\u30f3\u30d7\u30eb<\/a> (\u82f1\u8a9e)<\/span><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p><span style=\"font-family: arial, helvetica, sans-serif;\">\u30b5\u30f3\u30d7\u30eb\u3067\u306f\u3001\u4ee5\u4e0b\u306e\u30d5\u30ed\u30fc\u3092\u8a18\u8ff0\u3057\u3066\u3044\u307e\u3059\u3002<\/span><\/p>\n<p>&nbsp;<\/p>\n<table style=\"width: 652px; height: 360px;\" width=\"604\">\n<tbody>\n<tr style=\"height: 56px;\">\n<td style=\"width: 293.677px; height: 56px;\"><span style=\"font-family: arial, helvetica, sans-serif;\">\u30d5\u30ed\u30fc\u30bf\u30a4\u30d7<\/span><\/td>\n<td style=\"width: 342.323px; height: 56px;\"><span style=\"font-family: arial, helvetica, sans-serif;\">\u30a2\u30af\u30b7\u30e7\u30f3<\/span><\/td>\n<\/tr>\n<tr style=\"height: 120px;\">\n<td style=\"width: 293.677px; height: 120px;\"><span style=\"font-family: arial, helvetica, sans-serif;\">\u6a5f\u80fd\u7684\u306a\u6b63\u3057\u3055\u3092\u691c\u8a3c\u3059\u308b\u305f\u3081\u306e\u30a8\u30df\u30e5\u30ec\u30fc\u30b7\u30e7\u30f3\u30fb\u30d5\u30ed\u30fc<\/span><\/td>\n<td style=\"width: 342.323px; height: 120px;\"><span style=\"font-family: arial, helvetica, sans-serif;\">CPU \u30a8\u30df\u30e5\u30ec\u30fc\u30bf\u30fc\u4e0a\u3067\u30d7\u30ed\u30b0\u30e9\u30e0\u3092\u691c\u8a3c\u3059\u308b\u305f\u3081\u306b\u30b3\u30f3\u30d1\u30a4\u30eb\u3059\u308b\u3002<\/span><\/p>\n<p>&nbsp;<\/td>\n<\/tr>\n<tr style=\"height: 80px;\">\n<td style=\"width: 293.677px; height: 80px;\"><span style=\"font-family: arial, helvetica, sans-serif;\">\u6700\u9069\u5316\u30ec\u30dd\u30fc\u30c8\u3092\u95b2\u89a7\u3059\u308b\u305f\u3081\u306e RTL \u30d5\u30ed\u30fc<\/span><\/td>\n<td style=\"width: 342.323px; height: 80px;\"><span style=\"font-family: arial, helvetica, sans-serif;\">FPGA \u5408\u6210\u306e\u521d\u671f\u6bb5\u968e\u3067\u505c\u6b62\u3057\u3001\u30c7\u30b6\u30a4\u30f3\u306e\u30d1\u30d5\u30a9\u30fc\u30de\u30f3\u30b9\u30fb\u30dc\u30c8\u30eb\u30cd\u30c3\u30af\u3092\u77ed\u6642\u9593\u3067\u89e3\u6790\u3059\u308b\u3002<\/span><\/td>\n<\/tr>\n<tr style=\"height: 104px;\">\n<td style=\"width: 293.677px; height: 104px;\"><span style=\"font-family: arial, helvetica, sans-serif;\">FPGA \u30d3\u30c3\u30c8\u30b9\u30c8\u30ea\u30fc\u30e0\u3092\u751f\u6210\u3059\u308b\u30cf\u30fc\u30c9\u30a6\u30a7\u30a2\u751f\u6210\u30d5\u30ed\u30fc<\/span><\/td>\n<td style=\"width: 342.323px; height: 104px;\"><span style=\"font-family: arial, helvetica, sans-serif;\">FPGA \u306e\u30cf\u30fc\u30c9\u30a6\u30a7\u30a2\u30fb\u30d3\u30c3\u30c8\u30b9\u30c8\u30ea\u30fc\u30e0\u3092\u751f\u6210\u3057\u3001\u30db\u30b9\u30c8 (CPU) \u30d7\u30ed\u30b0\u30e9\u30e0\u306b\u5bfe\u3057\u3066\u30ea\u30f3\u30af\u3059\u308b\u3002<\/span><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p><span style=\"font-family: arial, helvetica, sans-serif;\">\u3053\u306e\u30b5\u30f3\u30d7\u30eb\u3067\u6271\u3046\u30ad\u30fc\u30b3\u30f3\u30bb\u30d7\u30c8:<\/span><\/p>\n<ul>\n<li><span style=\"font-family: arial, helvetica, sans-serif;\">DPC++ \u306e FPGA \u3078\u306e\u30b3\u30f3\u30d1\u30a4\u30eb\u306f\u3001CPU \u3084 GPU \u3068\u3069\u3046\u9055\u3046\u306e\u304b\u3001\u306a\u305c\u9055\u3046\u306e\u304b<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif;\">FPGA \u30c7\u30d0\u30a4\u30b9\u30a4\u30e1\u30fc\u30b8\u306e\u7a2e\u985e\u3068\u305d\u306e\u4f7f\u7528\u6642\u671f<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif;\">FPGA \u3092\u30bf\u30fc\u30b2\u30c3\u30c8\u306b\u3057\u305f\u30b3\u30f3\u30d1\u30a4\u30eb\u30fb\u30aa\u30d7\u30b7\u30e7\u30f3<\/span><\/li>\n<\/ul>\n<h3><span style=\"font-family: arial, helvetica, sans-serif;\">\u30b5\u30f3\u30d7\u30eb 2\uff1a\u958b\u767a\u6642\u9593\u306e\u77ed\u7e2e<\/span><\/h3>\n<p><span style=\"font-family: arial, helvetica, sans-serif;\">\u3053\u306e\u30b5\u30f3\u30d7\u30eb\u3067\u306f\u3001FPGA \u306e\u30b3\u30f3\u30d1\u30a4\u30eb\u30d5\u30ed\u30fc\u3067\u30c7\u30d0\u30a4\u30b9\u30ea\u30f3\u30af\u6a5f\u69cb\u3092\u4f7f\u7528\u3057\u3001\u958b\u767a\u6642\u9593\u3092\u77ed\u7e2e\u3059\u308b\u65b9\u6cd5\u3092\u7d39\u4ecb\u3057\u3066\u3044\u307e\u3059\u3002<\/span><\/p>\n<table style=\"width: 709px;\" width=\"604\">\n<tbody>\n<tr>\n<td style=\"width: 324.458px;\"><span style=\"font-family: arial, helvetica, sans-serif;\">CLI \u307e\u305f\u306f IDE \u30b5\u30f3\u30d7\u30eb\u540d<\/span><\/td>\n<td style=\"width: 368.542px;\"><span style=\"font-family: arial, helvetica, sans-serif;\">Git \u30ea\u30dd\u30b8\u30c8\u30ea\u30fc\u3078\u306e\u30ea\u30f3\u30af<\/span><\/td>\n<\/tr>\n<tr>\n<td style=\"width: 324.458px;\"><span style=\"font-family: arial, helvetica, sans-serif;\">fast_recompile<\/span><\/td>\n<td style=\"width: 368.542px;\"><span style=\"font-family: arial, helvetica, sans-serif;\"><a href=\"https:\/\/github.com\/oneapi-src\/oneAPI-samples\/tree\/master\/DirectProgramming\/DPC%2B%2BFPGA\/Tutorials\/GettingStarted\/fast_recompile\" target=\"_blank\" rel=\"noopener\">\u9ad8\u901f\u30ea\u30b3\u30f3\u30d1\u30a4\u30eb\u306e\u30b5\u30f3\u30d7\u30eb<\/a> (\u82f1\u8a9e)<\/span><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p><span style=\"font-family: arial, helvetica, sans-serif;\">\u30a4\u30f3\u30c6\u30eb<sup>\u00ae<\/sup> oneAPI DPC++\/C++ \u30b3\u30f3\u30d1\u30a4\u30e9\u30fc\u306f\u3001\u30b3\u30f3\u30d1\u30a4\u30eb\u6642\u306b FPGA \u30c7\u30d0\u30a4\u30b9\u30a4\u30e1\u30fc\u30b8\u304c\u751f\u6210\u3055\u308c\u308b\u3001FPGA \u7528\u306e\u5148\u884c\u30b3\u30f3\u30d1\u30a4\u30eb\u306e\u307f\u3092\u30b5\u30dd\u30fc\u30c8\u3057\u307e\u3059\u3002FPGA \u30c7\u30d0\u30a4\u30b9\u30a4\u30e1\u30fc\u30b8\u306e\u751f\u6210\u51e6\u7406\u306b\u306f\u6570\u6642\u9593\u304b\u304b\u308b\u3053\u3068\u304c\u3042\u308a\u307e\u3059\u3002\u305d\u306e\u305f\u3081\u3001\u30db\u30b9\u30c8\u30b3\u30fc\u30c9\u3068\u30c7\u30d0\u30a4\u30b9\u30b3\u30fc\u30c9\u304c\u4e00\u7dd2\u306b\u30b3\u30f3\u30d1\u30a4\u30eb\u3055\u308c\u3001\u30db\u30b9\u30c8\u30b3\u30fc\u30c9\u306b\u5909\u66f4\u304c\u3042\u3063\u305f\u5834\u5408\u3001\u30bd\u30fc\u30b9\u30b3\u30fc\u30c9\u5168\u4f53\u304c\u3053\u306e\u6642\u9593\u306e\u304b\u304b\u308b\u51e6\u7406\u306e\u5bfe\u8c61\u3068\u306a\u308a\u307e\u3059\u3002<\/span><\/p>\n<p><span style=\"font-family: arial, helvetica, sans-serif;\">\u30c7\u30d0\u30a4\u30b9\u30ea\u30f3\u30af\u6a5f\u69cb\u306b\u3088\u308a\u3001\u30c7\u30d0\u30a4\u30b9\u30b3\u30fc\u30c9\u306e\u30b3\u30f3\u30d1\u30a4\u30eb\u3068\u30db\u30b9\u30c8\u30b3\u30fc\u30c9\u306e\u30b3\u30f3\u30d1\u30a4\u30eb\u3092\u5206\u96e2\u3059\u308b\u3053\u3068\u304c\u3067\u304d\u307e\u3059\u3002\u30b3\u30fc\u30c9\u306e\u5909\u66f4\u304c\u30db\u30b9\u30c8\u306e\u307f\u306e\u30d5\u30a1\u30a4\u30eb\u306b\u306e\u307f\u9069\u7528\u3055\u308c\u308b\u5834\u5408\u3001FPGA \u30c7\u30d0\u30a4\u30b9\u30a4\u30e1\u30fc\u30b8\u306f\u518d\u751f\u6210\u3055\u308c\u305a\u3001\u9577\u3044\u30b3\u30f3\u30d1\u30a4\u30eb\u6642\u9593\u3092\u56de\u907f\u3059\u308b\u3053\u3068\u304c\u3067\u304d\u307e\u3059\u3002<\/span><\/p>\n<p><strong><span style=\"font-family: arial, helvetica, sans-serif;\">\u3053\u306e\u30b5\u30f3\u30d7\u30eb\u3067\u6271\u3046\u30ad\u30fc\u30b3\u30f3\u30bb\u30d7\u30c8:<\/span><\/strong><\/p>\n<ul>\n<li><span style=\"font-family: arial, helvetica, sans-serif;\">FPGA \u30d7\u30ed\u30b8\u30a7\u30af\u30c8\u3067\u30db\u30b9\u30c8\u3068\u30c7\u30d0\u30a4\u30b9\u306e\u30b3\u30fc\u30c9\u306e\u30b3\u30f3\u30d1\u30a4\u30eb\u3092\u5206\u3051\u308b\u3079\u304d\u7406\u7531<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif;\">-reuse-exe \u30d5\u30e9\u30b0\u306e\u4f7f\u7528\u65b9\u6cd5\u3068\u30c7\u30d0\u30a4\u30b9\u30ea\u30f3\u30af\u306e\u65b9\u6cd5<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif;\">\u30d7\u30ed\u30b8\u30a7\u30af\u30c8\u306b\u5fdc\u3058\u3066\u3069\u306e\u65b9\u5f0f\u3092\u9078\u629e\u3059\u308b\u304b<\/span><\/li>\n<\/ul>\n<h3><span style=\"font-family: arial, helvetica, sans-serif;\">\u30b5\u30f3\u30d7\u30eb 3\uff1a\u30ab\u30fc\u30cd\u30eb\u5f15\u6570\u306e\u30a8\u30a4\u30ea\u30a2\u30b7\u30f3\u30b0\u3092\u56de\u907f\u3059\u308b<\/span><\/h3>\n<p><span style=\"font-family: arial, helvetica, sans-serif;\">\u3053\u306e\u30b5\u30f3\u30d7\u30eb\u306f\u3001DPC++ [[intel::kernel_args_restrict]] \u30ab\u30fc\u30cd\u30eb\u5c5e\u6027\u306e\u4f7f\u7528\u3092\u793a\u3057\u3066\u304a\u308a\u3001\u30ab\u30fc\u30cd\u30eb\u5f15\u6570\u304c\u30a8\u30a4\u30ea\u30a2\u30b9\u3067\u306a\u3044\u3053\u3068\u3092\u4fdd\u8a3c\u3067\u304d\u308b\u5834\u5408\u306b\u9069\u7528\u3067\u304d\u307e\u3059 (C++ \u306e restrict \u3068\u985e\u4f3c\u3057\u3066\u3044\u307e\u3059)\u3002<\/span><\/p>\n<table style=\"width: 703px;\" width=\"604\">\n<tbody>\n<tr>\n<td style=\"width: 311.781px;\"><span style=\"font-family: arial, helvetica, sans-serif;\">CLI \u307e\u305f\u306f IDE \u30b5\u30f3\u30d7\u30eb\u540d<\/span><\/td>\n<td style=\"width: 375.219px;\"><span style=\"font-family: arial, helvetica, sans-serif;\">Git \u30ea\u30dd\u30b8\u30c8\u30ea\u30fc\u3078\u306e\u30ea\u30f3\u30af<\/span><\/td>\n<\/tr>\n<tr>\n<td style=\"width: 311.781px;\"><span style=\"font-family: arial, helvetica, sans-serif;\">kernel_args_restrict<\/span><\/td>\n<td style=\"width: 375.219px;\"><span style=\"font-family: arial, helvetica, sans-serif;\"><a href=\"https:\/\/github.com\/oneapi-src\/oneAPI-samples\/tree\/master\/DirectProgramming\/DPC%2B%2BFPGA\/Tutorials\/Features\/kernel_args_restrict\" target=\"_blank\" rel=\"noopener\">\u30ab\u30fc\u30cd\u30eb\u306e\u5f15\u6570\u3092\u5236\u9650\u3059\u308b\u30b5\u30f3\u30d7\u30eb<\/a> (\u82f1\u8a9e)<\/span><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p><span style=\"font-family: arial, helvetica, sans-serif;\">\u30dd\u30a4\u30f3\u30bf\u30fc\u30fb\u30a8\u30a4\u30ea\u30a2\u30b7\u30f3\u30b0\u306f\u3001\u540c\u3058\u30e1\u30e2\u30ea\u30fc\u4f4d\u7f6e\u306b\u7570\u306a\u308b\u540d\u524d (\u5909\u6570) \u3092\u4f7f\u3063\u3066\u30a2\u30af\u30bb\u30b9\u3057\u305f\u5834\u5408\u306b\u767a\u751f\u3057\u307e\u3059\u3002\u30dd\u30a4\u30f3\u30bf\u30fc\u30fb\u30a8\u30a4\u30ea\u30a2\u30b7\u30f3\u30b0\u306e\u305f\u3081\u3001\u30b3\u30f3\u30d1\u30a4\u30e9\u30fc\u306f\u3001\u30a8\u30a4\u30ea\u30a2\u30b9\u306e\u53ef\u80fd\u6027\u304c\u3042\u308b\u64cd\u4f5c\u306e\u4e26\u3079\u66ff\u3048\u3001\u4e26\u5217\u5316\u3001\u91cd\u8907\u5316\u3092\u884c\u3046\u6700\u9069\u5316\u306b\u3064\u3044\u3066\u4fdd\u5b88\u7684\u306b\u306a\u308a\u307e\u3059\u3002kernel_args_restrict \u5c5e\u6027\u3092\u4f7f\u7528\u3059\u308b\u3068\u3001\u3088\u308a\u7a4d\u6975\u7684\u306a\u30b3\u30f3\u30d1\u30a4\u30e9\u30fc\u6700\u9069\u5316\u304c\u53ef\u80fd\u306b\u306a\u308a\u3001FPGA \u4e0a\u306e\u30ab\u30fc\u30cd\u30eb\u30fb\u30d1\u30d5\u30a9\u30fc\u30de\u30f3\u30b9\u304c\u5411\u4e0a\u3059\u308b\u3053\u3068\u304c\u3088\u304f\u3042\u308a\u307e\u3059\u3002<\/span><\/p>\n<p><strong><span style=\"font-family: arial, helvetica, sans-serif;\">\u3053\u306e\u30b5\u30f3\u30d7\u30eb\u3067\u6271\u3046\u30ad\u30fc\u30b3\u30f3\u30bb\u30d7\u30c8:<\/span><\/strong><\/p>\n<ul>\n<li><span style=\"font-family: arial, helvetica, sans-serif;\">\u30dd\u30a4\u30f3\u30bf\u30fc\u30fb\u30a8\u30a4\u30ea\u30a2\u30b7\u30f3\u30b0\u306e\u554f\u984c\u3068\u30b3\u30f3\u30d1\u30a4\u30e9\u30fc\u306e\u6700\u9069\u5316\u306b\u304a\u3051\u308b\u305d\u306e\u5f71\u97ff<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif;\">kernel_args_restrict \u5c5e\u6027\u306e\u52d5\u4f5c\u3068\u30ab\u30fc\u30cd\u30eb\u3067\u4f7f\u7528\u3059\u308b\u5834\u5408\u306b\u3064\u3044\u3066<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif;\">\u3053\u306e\u5c5e\u6027\u304c FPGA \u4e0a\u3067\u306e\u30ab\u30fc\u30cd\u30eb\u306e\u30d1\u30d5\u30a9\u30fc\u30de\u30f3\u30b9\u306b\u4e0e\u3048\u308b\u5f71\u97ff<\/span><\/li>\n<\/ul>\n<h3><span style=\"font-family: arial, helvetica, sans-serif;\">\u30b5\u30f3\u30d7\u30eb 4\uff1a\u30eb\u30fc\u30d7\u306e\u30b9\u30eb\u30fc\u30d7\u30c3\u30c8\u3092\u5411\u4e0a\u3055\u305b\u308b\u3053\u3068\u306b\u3088\u308b\u6700\u9069\u5316<\/span><\/h3>\n<p><span style=\"font-family: arial, helvetica, sans-serif;\">\u3053\u306e\u30b5\u30f3\u30d7\u30eb\u3067\u306f\u3001DPC++ FPGA \u30d7\u30ed\u30b0\u30e9\u30e0\u306e\u30b9\u30eb\u30fc\u30d7\u30c3\u30c8\u3092\u5411\u4e0a\u3055\u305b\u308b\u305f\u3081\u306b\u30eb\u30fc\u30d7\u3092\u30a2\u30f3\u30ed\u30fc\u30eb\u3059\u308b\u7c21\u5358\u306a\u4f8b\u3092\u793a\u3057\u3066\u3044\u307e\u3059\u3002<\/span><\/p>\n<table style=\"width: 692px;\" width=\"604\">\n<tbody>\n<tr>\n<td style=\"width: 303.75px;\"><span style=\"font-family: arial, helvetica, sans-serif;\">CLI \u307e\u305f\u306f IDE \u30b5\u30f3\u30d7\u30eb\u540d<\/span><\/td>\n<td style=\"width: 372.25px;\"><span style=\"font-family: arial, helvetica, sans-serif;\">Git \u30ea\u30dd\u30b8\u30c8\u30ea\u30fc\u3078\u306e\u30ea\u30f3\u30af<\/span><\/td>\n<\/tr>\n<tr>\n<td style=\"width: 303.75px;\"><span style=\"font-family: arial, helvetica, sans-serif;\">loop_unroll<\/span><\/td>\n<td style=\"width: 372.25px;\"><span style=\"font-family: arial, helvetica, sans-serif;\"><a href=\"https:\/\/github.com\/oneapi-src\/oneAPI-samples\/tree\/master\/DirectProgramming\/DPC%2B%2BFPGA\/Tutorials\/Features\/loop_unroll\" target=\"_blank\" rel=\"noopener\">\u30eb\u30fc\u30d7\u30a2\u30f3\u30ed\u30fc\u30eb\u306e\u30b5\u30f3\u30d7\u30eb<\/a> (\u82f1\u8a9e)<\/span><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p><span style=\"font-family: arial, helvetica, sans-serif;\">\u30eb\u30fc\u30d7\u30a2\u30f3\u30ed\u30fc\u30eb\u306f\u3001\u30eb\u30fc\u30d7\u5185\u306e\u8a08\u7b97\u30ed\u30b8\u30c3\u30af\u3092\u8907\u88fd\u3059\u308b\u3053\u3068\u3067\u30d7\u30ed\u30b0\u30e9\u30e0\u306e\u4e26\u5217\u6027\u3092\u9ad8\u3081\u3001\u8a2d\u8a08\u306e\u30b9\u30eb\u30fc\u30d7\u30c3\u30c8\u3092\u5411\u4e0a\u3055\u305b\u308b\u3053\u3068\u304c\u3067\u304d\u308b\u4ed5\u7d44\u307f\u3067\u3059\u3002<\/span><\/p>\n<p><strong><span style=\"font-family: arial, helvetica, sans-serif;\">\u3053\u306e\u30b5\u30f3\u30d7\u30eb\u3067\u6271\u3046\u30ad\u30fc\u30b3\u30f3\u30bb\u30d7\u30c8:<\/span><\/strong><\/p>\n<ul>\n<li><span style=\"font-family: arial, helvetica, sans-serif;\">\u30eb\u30fc\u30d7\u30a2\u30f3\u30ed\u30fc\u30eb\u306e\u57fa\u672c<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif;\">\u30d7\u30ed\u30b0\u30e9\u30e0\u5185\u306e\u30eb\u30fc\u30d7\u3092\u30a2\u30f3\u30ed\u30fc\u30eb\u3059\u308b<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif;\">\u30d7\u30ed\u30b0\u30e9\u30e0\u306b\u9069\u3057\u305f\u30a2\u30f3\u30ed\u30fc\u30eb\u30d5\u30a1\u30af\u30bf\u30fc\u306e\u6c7a\u5b9a<\/span><\/li>\n<\/ul>\n<h3><span style=\"font-family: arial, helvetica, sans-serif;\">\u30b5\u30f3\u30d7\u30eb 5\uff1a\u30d1\u30a4\u30d7\u3092\u4f7f\u3063\u305f\u30c7\u30fc\u30bf\u8ee2\u9001<\/span><\/h3>\n<p><span style=\"font-family: arial, helvetica, sans-serif;\">\u3053\u306e\u30b5\u30f3\u30d7\u30eb\u306f\u3001\u30d1\u30a4\u30d7\u3068\u3044\u3046\u62bd\u8c61\u6982\u5ff5\u3092\u7528\u3044\u3066\u30ab\u30fc\u30cd\u30eb\u9593\u3067\u30c7\u30fc\u30bf\u3092\u8ee2\u9001\u3059\u308b\u65b9\u6cd5\u3092\u793a\u3057\u3066\u3044\u307e\u3059\u3002<\/span><\/p>\n<table style=\"width: 688px;\" width=\"604\">\n<tbody>\n<tr>\n<td style=\"width: 318.469px;\"><span style=\"font-family: arial, helvetica, sans-serif;\">CLI \u307e\u305f\u306f IDE \u30b5\u30f3\u30d7\u30eb\u540d<\/span><\/td>\n<td style=\"width: 353.531px;\"><span style=\"font-family: arial, helvetica, sans-serif;\">Git \u30ea\u30dd\u30b8\u30c8\u30ea\u30fc\u3078\u306e\u30ea\u30f3\u30af<\/span><\/td>\n<\/tr>\n<tr>\n<td style=\"width: 318.469px;\"><span style=\"font-family: arial, helvetica, sans-serif;\">pipes<\/span><\/td>\n<td style=\"width: 353.531px;\"><span style=\"font-family: arial, helvetica, sans-serif;\"><a href=\"https:\/\/github.com\/oneapi-src\/oneAPI-samples\/tree\/master\/DirectProgramming\/DPC%2B%2BFPGA\/Tutorials\/Features\/pipes\" target=\"_blank\" rel=\"noopener\">\u30d1\u30a4\u30d7\u306e\u30b5\u30f3\u30d7\u30eb<\/a> (\u82f1\u8a9e)<\/span><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p><strong><span style=\"font-family: arial, helvetica, sans-serif;\">\u3053\u306e\u30b5\u30f3\u30d7\u30eb\u3067\u6271\u3046\u30ad\u30fc\u30b3\u30f3\u30bb\u30d7\u30c8:<\/span><\/strong><\/p>\n<ul>\n<li><span style=\"font-family: arial, helvetica, sans-serif;\">FPGA \u5c02\u7528 DPC++ \u30d1\u30a4\u30d7\u62e1\u5f35\u306e\u57fa\u790e\u77e5\u8b58<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif;\">DPC++ \u30d7\u30ed\u30b0\u30e9\u30e0\u3067\u306e\u30d1\u30a4\u30d7\u306e\u5ba3\u8a00\u3068\u4f7f\u7528\u65b9\u6cd5<\/span><\/li>\n<\/ul>\n<h3><span style=\"font-family: arial, helvetica, sans-serif;\">\u30b5\u30f3\u30d7\u30eb 6\uff1a\u30c0\u30d6\u30eb\u30fb\u30d0\u30c3\u30d5\u30a1\u30ea\u30f3\u30b0\u306b\u3088\u308b\u6027\u80fd\u5411\u4e0a\u00a0<\/span><\/h3>\n<p><span style=\"font-family: arial, helvetica, sans-serif;\">\u672c\u30b5\u30f3\u30d7\u30eb\u306f\u3001\u30db\u30b9\u30c8\u5074\u306e\u51e6\u7406\u3068\u30db\u30b9\u30c8\u3068\u30c7\u30d0\u30a4\u30b9\u9593\u306e\u30d0\u30c3\u30d5\u30a1\u30fc\u8ee2\u9001\u3092\u30ab\u30fc\u30cd\u30eb\u5b9f\u884c\u3067\u4e26\u5217\u5316\u3057\u3001\u30a2\u30d7\u30ea\u30b1\u30fc\u30b7\u30e7\u30f3\u5168\u4f53\u306e\u30d1\u30d5\u30a9\u30fc\u30de\u30f3\u30b9\u3092\u5411\u4e0a\u3055\u305b\u308b\u65b9\u6cd5\u3092\u793a\u3057\u3066\u3044\u307e\u3059\u3002<\/span><\/p>\n<table style=\"width: 674px;\" width=\"604\">\n<tbody>\n<tr>\n<td style=\"width: 310.938px;\"><span style=\"font-family: arial, helvetica, sans-serif;\">CLI \u307e\u305f\u306f IDE \u30b5\u30f3\u30d7\u30eb\u540d<\/span><\/td>\n<td style=\"width: 347.062px;\"><span style=\"font-family: arial, helvetica, sans-serif;\">Git \u30ea\u30dd\u30b8\u30c8\u30ea\u30fc\u3078\u306e\u30ea\u30f3\u30af<\/span><\/td>\n<\/tr>\n<tr>\n<td style=\"width: 310.938px;\"><span style=\"font-family: arial, helvetica, sans-serif;\">double_buffering<\/span><\/td>\n<td style=\"width: 347.062px;\"><span style=\"font-family: arial, helvetica, sans-serif;\"><a href=\"https:\/\/github.com\/oneapi-src\/oneAPI-samples\/tree\/master\/DirectProgramming\/DPC%2B%2BFPGA\/Tutorials\/DesignPatterns\/double_buffering\" target=\"_blank\" rel=\"noopener\">\u30c0\u30d6\u30eb\u30fb\u30d0\u30c3\u30d5\u30a1\u30ea\u30f3\u30b0\u306e\u30b5\u30f3\u30d7\u30eb<\/a> (\u82f1\u8a9e)<\/span><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p><strong><span style=\"font-family: arial, helvetica, sans-serif;\">\u3053\u306e\u30b5\u30f3\u30d7\u30eb\u3067\u6271\u3046\u30ad\u30fc\u30b3\u30f3\u30bb\u30d7\u30c8:<\/span><\/strong><\/p>\n<ul>\n<li><span style=\"font-family: arial, helvetica, sans-serif;\">\u30c0\u30d6\u30eb\u30fb\u30d0\u30c3\u30d5\u30a1\u30ea\u30f3\u30b0\u6700\u9069\u5316\u6280\u8853<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif;\">\u30c0\u30d6\u30eb\u30fb\u30d0\u30c3\u30d5\u30a1\u30ea\u30f3\u30b0\u304c\u6709\u52b9\u306a\u5834\u5408\u306e\u5224\u65ad<\/span><\/li>\n<li><span style=\"font-family: arial, helvetica, sans-serif;\">\u30c0\u30d6\u30eb\u30fb\u30d0\u30c3\u30d5\u30a1\u30ea\u30f3\u30b0\u306e\u52b9\u679c\u3092\u6e2c\u5b9a\u3059\u308b\u65b9\u6cd5<\/span><\/li>\n<\/ul>\n<h2><span style=\"font-family: arial, helvetica, sans-serif;\">\u6b21\u306e\u30b9\u30c6\u30c3\u30d7<\/span><\/h2>\n<p><span style=\"font-family: arial, helvetica, sans-serif;\">\u4e0a\u8a18\u306e\u30b5\u30f3\u30d7\u30eb\u306b\u76ee\u3092\u901a\u3057\u305f\u5f8c\u3001\u4f9d\u5b58\u95a2\u4fc2\u56f3\u306b\u57fa\u3065\u3044\u3066\u6b8b\u308a\u306e DPC++ FPGA \u30b5\u30f3\u30d7\u30eb (\u30c1\u30e5\u30fc\u30c8\u30ea\u30a2\u30eb\u307e\u305f\u306f\u30ea\u30d5\u30a1\u30ec\u30f3\u30b9\u30fb\u30c7\u30b6\u30a4\u30f3) \u3092\u3054\u78ba\u8a8d\u3044\u305f\u3060\u3051\u307e\u3059\u3002\u30c1\u30e5\u30fc\u30c8\u30ea\u30a2\u30eb\u306e\u591a\u304f\u306f\u3001\u307b\u304b\u306e\u30c1\u30e5\u30fc\u30c8\u30ea\u30a2\u30eb\u306e\u30b3\u30f3\u30bb\u30d7\u30c8\u306b\u57fa\u3065\u3044\u3066\u4f5c\u3089\u308c\u3066\u3044\u308b\u3053\u3068\u306b\u6ce8\u610f\u3057\u3066\u304f\u3060\u3055\u3044\u3002\u307e\u305f\u3001\u6b21\u306e\u30ea\u30bd\u30fc\u30b9\u3082\u53c2\u7167\u3057\u3066\u304f\u3060\u3055\u3044\u3002<\/span><\/p>\n<table style=\"width: 617px;\">\n<tbody>\n<tr>\n<td style=\"width: 261.927px;\"><span style=\"font-family: arial, helvetica, sans-serif;\">\u30c9\u30ad\u30e5\u30e1\u30f3\u30c8\u00a0<\/span><\/td>\n<td style=\"width: 339.073px;\"><span style=\"font-family: arial, helvetica, sans-serif;\">\u8aac\u660e<\/span><\/td>\n<\/tr>\n<tr>\n<td style=\"width: 261.927px;\"><span style=\"font-family: arial, helvetica, sans-serif;\"><a href=\"https:\/\/devcloud.intel.com\/oneapi\/get-started\/base-toolkit\/\" target=\"_blank\" rel=\"noopener\">Get Started with Intel<sup>\u00ae<\/sup> oneAPI Base Toolkit on the DevCloud\u00a0<\/a><\/span><span style=\"font-family: arial, helvetica, sans-serif;\">(\u82f1\u8a9e)<\/span><\/td>\n<td style=\"width: 339.073px;\"><span style=\"font-family: arial, helvetica, sans-serif;\">\u30a4\u30f3\u30c6\u30eb<sup>\u00ae<\/sup> DevCloud \u958b\u767a\u30b5\u30f3\u30c9\u30dc\u30c3\u30af\u30b9\u56fa\u6709\u306e\u624b\u9806\u306b\u3064\u3044\u3066\u306f\u3001\u672c\u30ac\u30a4\u30c9\u3092\u53c2\u7167\u3057\u3066\u304f\u3060\u3055\u3044\u3002<\/span><\/td>\n<\/tr>\n<tr>\n<td style=\"width: 261.927px;\"><span style=\"font-family: arial, helvetica, sans-serif;\"><a href=\"https:\/\/software.intel.com\/content\/www\/us\/en\/develop\/documentation\/installation-guide-for-intel-oneapi-toolkits-linux\/top\/set-up-a-system-for-fpga-with-the-intel-pac.html\" target=\"_blank\" rel=\"noopener\">Installation Guide for Intel<sup>\u00ae<\/sup> oneAPI Toolkits\u00a0<\/a><\/span><span style=\"font-family: arial, helvetica, sans-serif;\">(\u82f1\u8a9e)<\/span><\/td>\n<td style=\"width: 339.073px;\"><span style=\"font-family: arial, helvetica, sans-serif;\">\u30a4\u30f3\u30c6\u30eb<sup>\u00ae<\/sup> oneAPI \u30d9\u30fc\u30b9\u30fb\u30c4\u30fc\u30eb\u30ad\u30c3\u30c8\u304a\u3088\u3073 oneAPI \u30d9\u30fc\u30b9\u30fb\u30c4\u30fc\u30eb\u30ad\u30c3\u30c8\u7528\u30a4\u30f3\u30c6\u30eb<sup>\u00ae<\/sup> FPGA \u30a2\u30c9\u30aa\u30f3\u306e\u30a4\u30f3\u30b9\u30c8\u30fc\u30eb\u306b\u3064\u3044\u3066\u8aac\u660e\u3057\u307e\u3059\u3002<\/span><\/td>\n<\/tr>\n<tr>\n<td style=\"width: 261.927px;\"><span style=\"font-family: arial, helvetica, sans-serif;\"><a href=\"https:\/\/software.intel.com\/content\/www\/us\/en\/develop\/documentation\/oneapi-programming-guide\/top.html\" target=\"_blank\" rel=\"noopener\">Intel<sup>\u00ae<\/sup> oneAPI Programming Guide\u00a0<\/a><\/span><span style=\"font-family: arial, helvetica, sans-serif;\">(\u82f1\u8a9e)<\/span><\/td>\n<td style=\"width: 339.073px;\"><span style=\"font-family: arial, helvetica, sans-serif;\">oneAPI \u3068 DPC++ \u306b\u3064\u3044\u3066\u3001\u30d7\u30ed\u30b0\u30e9\u30df\u30f3\u30b0\u30fb\u30e2\u30c7\u30eb\u3001\u30d7\u30ed\u30b0\u30e9\u30df\u30f3\u30b0\u30fb\u30a4\u30f3\u30bf\u30fc\u30d5\u30a7\u30a4\u30b9\u3001DPC++ \u8a00\u8a9e\u3068\u30e9\u30f3\u30bf\u30a4\u30e0\u3001API\u3001\u30bd\u30d5\u30c8\u30a6\u30a7\u30a2\u958b\u767a\u30d7\u30ed\u30bb\u30b9\u306b\u3064\u3044\u3066\u5b66\u3073\u307e\u3059\u3002<\/span><\/td>\n<\/tr>\n<tr>\n<td style=\"width: 261.927px;\"><span style=\"font-family: arial, helvetica, sans-serif;\"><a href=\"https:\/\/software.intel.com\/content\/www\/us\/en\/develop\/documentation\/oneapi-fpga-optimization-guide\/top.html\" target=\"_blank\" rel=\"noopener\">Intel<sup>\u00ae<\/sup> oneAPI DPC++ FPGA Optimization Guide\u00a0<\/a><\/span><span style=\"font-family: arial, helvetica, sans-serif;\">(\u82f1\u8a9e)<\/span><\/td>\n<td style=\"width: 339.073px;\"><span style=\"font-family: arial, helvetica, sans-serif;\">DPC++ \u306e\u6a5f\u80fd\u304a\u3088\u3073\u57fa\u790e\u3068\u306a\u308b\u30cf\u30fc\u30c9\u30a6\u30a7\u30a2\u3092\u6d3b\u7528\u3057\u3001\u30c7\u30b6\u30a4\u30f3\u3092 FPGA \u306b\u6700\u9069\u5316\u3059\u308b\u65b9\u6cd5\u306b\u3064\u3044\u3066\u8aac\u660e\u3057\u307e\u3059\u3002<\/span><\/td>\n<\/tr>\n<tr>\n<td style=\"width: 261.927px;\"><span style=\"font-family: arial, helvetica, sans-serif;\"><a href=\"https:\/\/software.intel.com\/content\/www\/us\/en\/develop\/documentation\/get-started-with-intel-oneapi-base-linux\/top.html\" target=\"_blank\" rel=\"noopener\">Get Started with the Intel<sup>\u00ae<\/sup> oneAPI Base Toolkit for Linux*\u00a0<\/a><\/span><span style=\"font-family: arial, helvetica, sans-serif;\">(\u82f1\u8a9e)<\/span><\/td>\n<td style=\"width: 339.073px;\"><span style=\"font-family: arial, helvetica, sans-serif;\">Linux* \u306e\u30b9\u30bf\u30fc\u30c8\u30a2\u30c3\u30d7\u306e\u624b\u9806\u306f\u3001\u3053\u306e\u30ac\u30a4\u30c9\u3092\u53c2\u7167\u3057\u3066\u304f\u3060\u3055\u3044\u3002<\/span><\/td>\n<\/tr>\n<tr>\n<td style=\"width: 261.927px;\"><span style=\"font-family: arial, helvetica, sans-serif;\"><a href=\"https:\/\/software.intel.com\/content\/www\/us\/en\/develop\/documentation\/get-started-with-intel-oneapi-base-windows\/top.html\" target=\"_blank\" rel=\"noopener\">Get Started with the Intel<sup>\u00ae<\/sup> oneAPI Base Toolkit for Windows*\u00a0<\/a><\/span><span style=\"font-family: arial, helvetica, sans-serif;\">(\u82f1\u8a9e)<\/span><\/td>\n<td style=\"width: 339.073px;\"><span style=\"font-family: arial, helvetica, sans-serif;\">Windows* \u306e\u30b9\u30bf\u30fc\u30c8\u30a2\u30c3\u30d7\u306e\u624b\u9806\u306f\u3001\u3053\u306e\u30ac\u30a4\u30c9\u3092\u53c2\u7167\u3057\u3066\u304f\u3060\u3055\u3044\u3002<\/span><\/td>\n<\/tr>\n<tr>\n<td style=\"width: 261.927px;\"><span style=\"font-family: arial, helvetica, sans-serif;\"><a href=\"https:\/\/github.com\/oneapi-src\/oneAPI-samples\/tree\/master\/DirectProgramming\/DPC%2B%2BFPGA\" target=\"_blank\" rel=\"noopener\">FPGA\u00a0Tutorials\u00a0\u00a0<\/a><\/span><span style=\"font-family: arial, helvetica, sans-serif;\">(\u82f1\u8a9e)<\/span><\/td>\n<td style=\"width: 339.073px;\"><span style=\"font-family: arial, helvetica, sans-serif;\">\u30c1\u30e5\u30fc\u30c8\u30ea\u30a2\u30eb\u306e\u8a73\u3057\u3044\u4f7f\u3044\u65b9\u306f\u3001\u3053\u3061\u3089\u306e\u30c1\u30e5\u30fc\u30c8\u30ea\u30a2\u30eb\u3092\u53c2\u7167\u3057\u3066\u304f\u3060\u3055\u3044\u3002<\/span><\/td>\n<\/tr>\n<tr>\n<td style=\"width: 261.927px;\"><span style=\"font-family: arial, helvetica, sans-serif;\"><a href=\"https:\/\/software.intel.com\/content\/www\/us\/en\/develop\/articles\/dpcpp-foundations-code-sample.html\" target=\"_blank\" rel=\"noopener\">DPC++ Foundations Code Sample Walk-Through\u00a0<\/a><\/span><span style=\"font-family: arial, helvetica, sans-serif;\">(\u82f1\u8a9e)<\/span><\/td>\n<td style=\"width: 339.073px;\"><span style=\"font-family: arial, helvetica, sans-serif;\">\u30c7\u30fc\u30bf\u4e26\u5217\u51e6\u7406 C++ (DPC++) \u306e\u57fa\u790e\u306b\u95a2\u3059\u308b\u30b3\u30fc\u30c9\u306e\u30a6\u30a9\u30fc\u30af\u30b9\u30eb\u30fc\u306f\u3001\u3053\u306e\u30ac\u30a4\u30c9\u3092\u53c2\u7167\u3057\u3066\u304f\u3060\u3055\u3044\u3002<\/span><\/td>\n<\/tr>\n<tr>\n<td style=\"width: 261.927px;\"><span style=\"font-family: arial, helvetica, sans-serif;\"><a href=\"https:\/\/www.intel.com\/content\/www\/us\/en\/programmable\/support\/training\/catalog.html?keywords=oneAPI\" target=\"_blank\" rel=\"noopener\">FPGA oneAPI Training\u00a0<\/a><\/span><span style=\"font-family: arial, helvetica, sans-serif;\">(\u82f1\u8a9e)<\/span><\/td>\n<td style=\"width: 339.073px;\"><span style=\"font-family: arial, helvetica, sans-serif;\">\u30c8\u30ec\u30fc\u30cb\u30f3\u30b0\u30fb\u30b5\u30a4\u30c8\u3067\u306f\u3001\u30a6\u30a7\u30d3\u30ca\u30fc\u3084\u30af\u30a4\u30c3\u30af\u30d3\u30c7\u30aa\u3092\u3054\u89a7\u3044\u305f\u3060\u3051\u307e\u3059\u3002<\/span><\/td>\n<\/tr>\n<tr>\n<td style=\"width: 261.927px;\"><span style=\"font-family: arial, helvetica, sans-serif;\"><a href=\"https:\/\/www.khronos.org\/registry\/SYCL\/specs\/sycl-1.2.1.pdf\" target=\"_blank\" rel=\"noopener\">SYCL Specification (v 1.2.1)\u00a0<\/a><\/span><span style=\"font-family: arial, helvetica, sans-serif;\">(\u82f1\u8a9e)<\/span><\/td>\n<td style=\"width: 339.073px;\"><span style=\"font-family: arial, helvetica, sans-serif;\">Khronos \u793e\u306e SYCL* \u4ed5\u69d8\u30d0\u30fc\u30b8\u30e7\u30f3 1.2.1 \u3067\u3059\u3002<\/span><\/td>\n<\/tr>\n<tr>\n<td style=\"width: 261.927px;\"><span style=\"font-family: arial, helvetica, sans-serif;\"><a href=\"https:\/\/link.springer.com\/book\/10.1007%2F978-1-4842-5574-2\" target=\"_blank\" rel=\"noopener\">Data Parallel C++: Mastering DPC++ for Programming of Heterogeneous Systems Using C++ and SYCL\u00a0<\/a><\/span><span style=\"font-family: arial, helvetica, sans-serif;\">(\u82f1\u8a9e)<\/span><\/td>\n<td style=\"width: 339.073px;\"><span style=\"font-family: arial, helvetica, sans-serif;\">\u30c7\u30fc\u30bf\u4e26\u5217\u51e6\u7406\u3092\u7528\u3044\u305f C++ \u30d7\u30ed\u30b0\u30e9\u30e0\u306e\u9ad8\u901f\u5316\u624b\u6cd5\u3092\u5b66\u3079\u308b\u30b5\u30fc\u30c9\u30d1\u30fc\u30c6\u30a3\u30fc\u30fb\u30aa\u30fc\u30d7\u30f3\u30fb\u30a2\u30af\u30bb\u30b9\u30d6\u30c3\u30af\u3067\u3059\u3002\u672c\u66f8\u306f\u3001\u30b3\u30f3\u30d4\u30e5\u30fc\u30c6\u30a3\u30f3\u30b0\u3092\u65b0\u305f\u306a\u30ec\u30d9\u30eb\u3078\u3068\u62bc\u3057\u4e0a\u3052\u308b\u3001\u3053\u306e\u30d1\u30ef\u30d5\u30eb\u3067\u91cd\u8981\u306a\u65b0\u958b\u767a\u306e\u6700\u524d\u7dda\u306b\u7acb\u3064\u3053\u3068\u3092\u53ef\u80fd\u306b\u3057\u307e\u3059\u3002\u5b9f\u7528\u7684\u306a\u30a2\u30c9\u30d0\u30a4\u30b9\u3001\u8a73\u7d30\u306a\u8aac\u660e\u3001\u4e3b\u8981\u306a\u30c8\u30d4\u30c3\u30af\u3092\u8aac\u660e\u3059\u308b\u30b3\u30fc\u30c9\u4f8b\u306a\u3069\u304c\u6e80\u8f09\u3067\u3059\u3002<\/span><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p><span style=\"font-family: arial, helvetica, sans-serif;\">oneAPI \u30d9\u30fc\u30b9\u30fb\u30c4\u30fc\u30eb\u30ad\u30c3\u30c8\u7528\u30a4\u30f3\u30c6\u30eb<sup>\u00ae<\/sup> FPGA \u30a2\u30c9\u30aa\u30f3\u306b\u95a2\u3059\u308b\u8a73\u7d30\u306f\u4ee5\u4e0b\u306e\u30dc\u30bf\u30f3\u304b\u3089\u3054\u89a7\u3044\u305f\u3060\u3051\u307e\u3059\u3002<\/span><\/p>\n<p><a href=\"https:\/\/www.xlsoft.com\/jp\/products\/intel\/oneapi\/fpga\/index.html\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter size-full wp-image-1267\" src=\"https:\/\/www.xlsoft.com\/jp\/blog\/intel\/wp-content\/uploads\/sites\/5\/2021\/09\/intel_blog_button.png\" alt=\"\" width=\"295\" height=\"65\" \/><\/a><\/p>\n<hr \/>\n<p><span style=\"font-family: arial, helvetica, sans-serif;\">\u53c2\u7167\u8a18\u4e8b: <a href=\"https:\/\/www.intel.com\/content\/www\/us\/en\/developer\/articles\/code-sample\/explore-dpcpp-through-intel-fpga-code-samples.html\" target=\"_blank\" rel=\"noopener\">Explore DPC++ Through Intel<sup>\u00ae<\/sup> FPGA Code Samples<\/a>\u00a0<\/span><\/p>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<div class=\"mh-excerpt\"><p>\u306f\u3058\u3081\u306b \u3053\u306e\u30ac\u30a4\u30c9\u306f\u3001\u6b21\u306e\u3053\u3068\u3092\u7406\u89e3\u3057\u3066\u3044\u305f\u3060\u304f <a class=\"mh-excerpt-more\" href=\"https:\/\/www.xlsoft.com\/jp\/blog\/intel\/2022\/02\/11\/explore-dpcpp-through-intel-fpga-code-samples\/\" title=\"\u30a4\u30f3\u30c6\u30eb FPGA \u30b3\u30fc\u30c9\u30b5\u30f3\u30d7\u30eb\u3067 DPC++ \u3092\u5b66\u3076\">[&#8230;]<\/a><\/p>\n<\/div>","protected":false},"author":1,"featured_media":1725,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[1],"tags":[26,17,70,9,14,8,71],"class_list":["post-1721","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-1","tag-dpc","tag-fpga","tag-inel-oneapi","tag-intel","tag-oneapi","tag-8","tag-71"],"aioseo_notices":[],"_links":{"self":[{"href":"https:\/\/www.xlsoft.com\/jp\/blog\/intel\/wp-json\/wp\/v2\/posts\/1721","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.xlsoft.com\/jp\/blog\/intel\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.xlsoft.com\/jp\/blog\/intel\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.xlsoft.com\/jp\/blog\/intel\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.xlsoft.com\/jp\/blog\/intel\/wp-json\/wp\/v2\/comments?post=1721"}],"version-history":[{"count":13,"href":"https:\/\/www.xlsoft.com\/jp\/blog\/intel\/wp-json\/wp\/v2\/posts\/1721\/revisions"}],"predecessor-version":[{"id":1955,"href":"https:\/\/www.xlsoft.com\/jp\/blog\/intel\/wp-json\/wp\/v2\/posts\/1721\/revisions\/1955"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.xlsoft.com\/jp\/blog\/intel\/wp-json\/wp\/v2\/media\/1725"}],"wp:attachment":[{"href":"https:\/\/www.xlsoft.com\/jp\/blog\/intel\/wp-json\/wp\/v2\/media?parent=1721"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.xlsoft.com\/jp\/blog\/intel\/wp-json\/wp\/v2\/categories?post=1721"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.xlsoft.com\/jp\/blog\/intel\/wp-json\/wp\/v2\/tags?post=1721"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}